| Sr FPGA Design Engineer at Remote, Remote, USA |
| Email: [email protected] |
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http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=1147897&uid= From: Rosalin, GLOBAL IT FAMILY LLC [email protected] Reply to: [email protected] Job ID 482764 Title - Sr FPGA Engineer Location 4562 E Mallory Cir HGR 116, Mesa, AZ 85215, USA (onsite only) Experience 7 to 10 years Job Description: 7+ years of FPGA design principles. 5+ years Working with Xilinx/Altera FPGA. Must have done RTL synthesis, constraints design, timing closure Must have experience with design and test bench development to verify the RTL design using Verilog, VHDL or SV/UVM Must have DO-254 and Aerospace background with SV/UVM skills Must be able to develop Communications and fault logging CPLD/FPGA design. Must have experience in developing PHAC, HDP, Requirements capture, design documentation Must have hands-on experience with Cadence or Synopsys tool, Microsemi Libero or Xilinx Vivado tool. Familiar with SCRUM/Sprint JIRA process. Qualification: BE Thanks & Regards, Rosalin Palo Global IT Family Email: [email protected] www.globalitfamily.com Keywords: information technology Arizona Idaho http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=1147897&uid= |
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| 11:22 PM 22-Feb-24 |