| Excellent Contract job opportunity for Design verification Engineer at Mountain View, CA (Onsite) at Mountain View, California, USA |
| Email: [email protected] |
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http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=124450&uid= From: Arti Singh, E-solutions [email protected] Reply to: [email protected] Hi, Please review my open it requirement and let me know your interest. Role: Design verification Engineer Location: Mountain View, CA Duration: Contract For Job description, Key words - Design verification - UVM - Low power - ARM , AXI, APB, AHB .. - UPF - Gate Level Simulation GLS - At least 7-8 years of experience with pre-silicon DV. - Knowledge and hands on experience with Verilog, System Verilog , UVM, debugging waveforms . - Must be proficient with : building a testbench for a medium complexity block using System Verilog and UVM . - Writing random tests, directed tests, error tests & performance tests for a block of medium complexity using System Verilog and UVM. - Developing, maintaining and supporting of the UVM verification environment. - Debugging tests with design engineers to deliver functionally correct design blocks . - OOPS, randomization, constraints, interfaces writing & analyzing functional coverage, assertions . - Generating and analyzing code coverage Thanks and Regards, Arti Singh IT Recruiter P:405-422-4060: E: [email protected] 2N Market St, Suite # 400, San Jose, CA- 95113 www.e-solutionsinc.com http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=124450&uid= |
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| 10:40 PM 08-Nov-22 |