| Design Verification engineer (HDL, SystemVerilog)--Folsom, CA (On-Site) at Folsom, Louisiana, USA |
| Email: [email protected] |
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http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=1420064&uid= Passport Number is Mandatory Hi, Greetings From Ampstek !! We are a Global staffing firm and we are Tier 1 vendor for all requirements and we can close positions immediately. Please review our job opening below and kindly send us the updated resume ASAP along with the details of consultants; Please add [email protected] in your distribution list Role Design Verification engineer (HDL, SystemVerilog) Location Folsom, CA (On-Site) Long-term Contract. Job Description: Utilize hands-on experience in System Verilog, UVM, and Testbench development to facilitate the verification process. Perform thorough debugging and troubleshooting to identify and resolve issues efficiently. Conduct full-chip and SoC simulations to validate design functionality and performance. Demonstrate expertise in subsystem verification, encompassing controllers and PHY components. Verify bus interfaces, controllers, and PHYs to guarantee seamless integration and functionality. Ideally, possess experience with subsystems/IPs such as DDR5, LPDDR, PCIe, Ethernet, UCIe. Thanks, and Regards Amiksha Sharma [email protected] (E-mail is the best way to reach me) https://www.linkedin.com/in/amikshasharma/ Ampstek Global IT Partner See what's happening on our social sites Organization Name | 103 Carnegie Center Drive, Suite 300, | Princeton, NJ 08540 US | Update Profile | Constant Contact Data Notice Keywords: information technology California New Jersey Design Verification engineer (HDL, SystemVerilog)--Folsom, CA (On-Site) [email protected] http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=1420064&uid= |
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| 01:45 AM 23-May-24 |