| Urgent Hiring :: DFT Engineer :: Santa Clara (US:95051), CA (Onsite) at Remote, Remote, USA |
| Email: [email protected] |
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http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=1534907&uid= Hello, I hope you are doing good, I have the below open position with our client, please find the job description below and let me know if youre interested, please send me a copy of your updated resume ASAP. Job Title: DFT Engineer Job Type: Contract Job Location: Santa Clara (US:95051), CA (Onsite) Job Description: 8+ years of hands-on experience with DFT and test flow with commercial EDA tools (Synopsys, Mentor) for large and complex SoCs. Strong fundamental knowledge of DFT techniques including JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST, LBIST. Experience with Synopsys DFT Complier, Tetramax, and VCS is required . Experience with TestMaxDFT, SMS, and TestMaxAdvisor tool suite is a plus. Experience in RTL simulation, synthesis, Linting, CDC checks, STA, DFT, quality metrics Hands-on expertise in writing System Verilog and VHDL Hands-on in Perl/Tcl/Python/Unix scripting Excellent analytical, and problem-solving skills 6+ years industry experience, masters degree or equivalent in EE or Computer Engineering (CE) Roles & Responsibilities: Provide SoC (top) level constraints and partitions for RTL/Logic designers, floorplan & PD engineers, DFT requirements Perform top/block-level DFT insertion including scan compression, boundary scan, JTAG, IEEE 1500 wrapper, MBIST, LBIST, ATPG and pattern simulation. Verify DFT circuitry and interface with other blocks, debug timing simulation issues. Closely work with physical design team to generate and validate timing constraints. Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning. Be able to work independently and own the complete task from DFT specification to final pattern delivery for sub-system and/or SOC. Working closely with synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power, and area goals, functional and diagnostics test coverage Ability to lead/manage a team, with active technical interaction with engineering teams Education: BSEE, in Electrical/Computer) OR (MSEE, in (Electrical/Computer) Expertise in DFT architecture, ATPG, Scan, JTAG, Clocking and Perl/TCL Scripting and Synthesis DFT Insertion . 2nd important skill Test Coverage Analysis, Compression, Boundary Scan. Need strong simulation experience with VCS/NCSIM. The use of Cadence DFT tools is a must Mandatory Skills is strong communication and leadership skills in addition the Technical -- Thanks and Regards, Aditya Srivastava E-mail Id: [email protected] -- -- Keywords: information technology container edition California Idaho Urgent Hiring :: DFT Engineer :: Santa Clara (US:95051), CA (Onsite) [email protected] http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=1534907&uid= |
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| 12:37 AM 04-Jul-24 |