| Urgent Hiring:: Design Verification Engineer:: Santa Clara, CA (Onsite) at Santa Clara, California, USA |
| Email: [email protected] |
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http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=1556400&uid= Hello, I hope you are doing good, I have the below open position with our client, please find the job description below and let me know if youre interested, please send me a copy of your updated resume ASAP. Job Title: Design Verification Engineer Job Type: Contract Job Location: Santa Clara, CA (Onsite) Job Description: Responsibilities: Architect and Create verification environments using System-Verilog and Universal verification methodology- UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces . Develop test plans and coverage metrics from specifications and writing block and chip-level tests. Create PERL/Python scripts to automate creating verification environments, test generation and debugging . Failure analysis of Register Transfer Level and Gate simulations and resolve them by working with design engineers. Create low-power test cases using UPF or CPF to verify the desired power intent of the SoC. Work with architects to determine the use-case scenarios to simulate Preferred Qualifications: 7+ years of experience in pre-silicon design verification Proficiency in C-shell scripting, Verilog-HDL & System Verilog . Strong knowledge of SV Assertions, UVM/OVM, and functional code coverage . SOC Verification experience using an ARM Cortex Microcontroller is required. Experience with advanced peripheral bus Verification IPs such as GPIO, UART, SPI, SW, JTAG, and I2C . Proficient with Cadence tools such as NCVerilog, NCSIM, and Simvision. Experience with linting tools (i.e Spyglass) will be helpful. Exposure to SDF annotated simulations with a good understanding of parasitic delays and timings is required. Exposure to FPGA programming and FPGA tools will be helpful. Independent, self-motivated with good analytical & communication skills. UVM/OVM/SystemVerilog/Python/C/C++ -- Thanks and Regards, Aditya Srivastava E-mail Id: [email protected] -- Keywords: cprogramm cplusplus information technology California Idaho Urgent Hiring:: Design Verification Engineer:: Santa Clara, CA (Onsite) [email protected] http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=1556400&uid= |
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| 07:19 PM 12-Jul-24 |