| Physical Design (PnR): Bay Area CA Onsite at Bay, Arkansas, USA |
| Email: [email protected] |
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http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=1689566&uid= From: pritam Singh, kpg99 [email protected] Reply to: [email protected] Hello, Job Title: Physical Design (PnR) Location: Bay Area, CA (Day 1Onsite) Duration: 6+ Months Contract Client : Marvel JD: 5-10 Years Tape out experience in block level and full chip floorplan/full chip partitioning flow. Experience in independently analyzing/resolving congestion, timing issues and basic understanding of clock tree build Timing understanding to independently analyze timing paths Experience in 16/14nm or below flows. Experience in die-size estimation spread sheet IP based and synthesis based Experience in IO/Bump planning & placement, custom analog/PG planning and route implementation Equivalence check understanding. Good to have Conformal LEC experience Experience in ICC2/Innovus/DC tools Experience in RDL routing Experience in interfacing with cross functional teams and block PnR teams Good understanding of basic shell scripting, tool based TCL scripting to automate all custom activities Experience in version control systems Experience in managing/mentoring small teams Thanks and Regards, Pritam Singh Sr. Technical Recruiter | KPG99 .INC Keywords: California Physical Design (PnR): Bay Area CA Onsite [email protected] http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=1689566&uid= |
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| 01:06 AM 24-Aug-24 |