| DSP Systems Engineer -ASIC or physical designer with Synthesis || San Jose, CA || Hybrid at San Jose, California, USA |
| Email: [email protected] |
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From: Roopesh Sharma, VIZON INC [email protected] Reply to: [email protected] Hello, Hope you are doing great. Please response me on my official email - [email protected] Please ensure that the resume does not exceed 5 pages. Job Title - DSP Systems Engineer - It is for an ASIC / physical designer who specializes in Synthesis Location - San Jose, CA - Hybrid Feedback on subs weve sent down. IR Sub-Interview Ruled out- Hung is good at general RTL engineer. I was hoping that he had extensive experience with Tensilica and more DSP blocks. Lets look for more DSP experience. LK Sub-Eric is a general RTL engineer. We need someone that has experience with PHY layer design or DSP blocks that are in WiFi, GNSS, BLE, chips. Not necessarily designing DSP algorithms but with RTL design experience related to those blocks. TB Sub- More on Firmware and a bit of RTL but not relevant DSP experience. NP Sub- No he is an FPGA engineer but no experience in the hardwire DSP engine designs that we are dealing with. NP-Ruled out Must have the linkedln DSP Systems Engineer Job Description We are looking for a qualified and highly motivated candidate for the development of signal processing RTL blocks and subsequent implementations. This will be a hands-on position, designing/implementing critical DSP blocks. Requirements MS or PhD degree emphasis in ASIC and DSP design Five or more years of experience in RTL design using Verilog and System Verilog Experience in developing & optimizing DSP related RTL blocks and test and verification of DSP blocks Previous exposure to physical layer of communication chips such as Wi-Fi, BLE, GNSS, or cellular is a plus Design of state machines, data paths, arbitration, and clock domain crossing logic Logic synthesis support, FPGA implementation, Timing constraints Exposure to Design for Test, understanding of scan concept and writing DFT friendly RTL Unified Power Format for simulation, synthesis, and electrical rule checking Equivalence checking Accurate power estimation for RTL blocks Committed to producing high-quality design Team player and excellent interpersonal, communication and writing skills Keywords: information technology microsoft California Wisconsin DSP Systems Engineer -ASIC or physical designer with Synthesis || San Jose, CA || Hybrid [email protected] |
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| 10:07 PM 26-Dec-24 |