| Looking On-site || ASIC STA and CAD Methodology Expertise || Longmont, CO (Onsite) at Longmont, Colorado, USA |
| Email: [email protected] |
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From: Gaurav, Quantum World IT [email protected] Reply to: [email protected] Greeting, I hope all is well with you For the following, Quantum World IT is seeking the best consultant profile. Please respond with your most recent resume if you are considering new opportunities. Looking On-site || ASIC STA and CAD Methodology Expertise || Longmont, CO (Onsite) Role name: | Developer | Role Description: | KEY RESPONSIBILITIES: Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs. Owning timing flow and execution to meet SoC timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management Engaging closely with block and SoC design teams to understand the design requirements, STA constraints, and convergence challenges. Engaging closely with physical implementation teams to ensure designs meet QoR and debug timing failures PREFERRED EXPERIENCE: 10+ years of professional experience in ASIC implementation and CAD methodology, preferably experience closing timing of high performance designs. Demonstrated ability in areas of ASIC STA constraints generation, timing analysis, timing convergence, and ECOs, at both block and full chip level, is a must Implementation experience and knowledge handling multi-voltage design is expected. STA closure of low power and multi-power mode designs is an added advantage. Expertise in industry standard ASIC EDA tools, including Synopsys DC and Primetime is required. Proficiency in scripting language, such as, TCL, Perl and/or Python Experience developing scripts to automate design flow, analysis Hands-on experience with Physical Design implementation is a plus Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams Strong analytical/problem solving skills and pronounced attention to details | Competencies: | EIS : ASIC Frontend - Modeling, RTL design and Implementation | Please enter the following information is needed for submission and Photo id Position Applied for | | Candidate Full Name [As per Passport] | | Contact Number Primary & Secondary | | Email ID | | Current Location | | Work Authorization | | Had ever worked with TCS in Past (Required filed) | | Are you comfortable for on-site | | Had you gotten covid vaccination doses | | Rate expectation | | Gauarv Kumar Phone: +1 8053915957 Email: [email protected] Quantum World Technologies Inc. 4281 Katella Ave, Suite #102 Los Alamitos CA 90720 USA Keywords: information technology California Colorado Idaho Looking On-site || ASIC STA and CAD Methodology Expertise || Longmont, CO (Onsite) [email protected] |
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| 08:29 PM 30-Jan-25 |