| ASIC Static Timing Analysis Engineer || Longmont, CO- Onsite at Longmont, Colorado, USA |
| Email: [email protected] |
|
Hello, Hope you are doing good...! This is Divya from Siri Info Solutions. I have some urgent requirements with one of my clients. Please go through the Job Description and let me know your interest. In case you are not interested, it will be nice to let your friends/colleagues know of this position who may be a potential. COMPLETE JOB DESCRIPTION IS BELOW FOR YOUR REVIEW: Job Title: ASIC Static Timing Analysis Engineer Location: Longmont, CO- Onsite Hire Type: Contract Skills: ASIC STA and CAD Methodology Expertise for High-Performance Design Implementation and Timing Closure KEY RESPONSIBILITIES: Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs. Owning timing flow and execution to meet SoC timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management Engaging closely with block and SoC design teams to understand the design requirements, STA constraints, and convergence challenges. Engaging closely with physical implementation teams to ensure designs meet QoR and debug timing failures PREFERRED EXPERIENCE: 10+ years of professional experience in ASIC implementation and CAD methodology, preferably experience closing timing of high performance designs. Demonstrated ability in areas of ASIC STA constraints generation, timing analysis, timing convergence, and ECOs, at both block and full chip level, is a must Implementation experience and knowledge handling multi-voltage design is expected. STA closure of low power and multi-power mode designs is an added advantage. Expertise in industry standard ASIC EDA tools, including Synopsys DC and Primetime is required. Proficiency in scripting language, such as, TCL, Perl and/or Python Experience developing scripts to automate design flow, analysis Hands-on experience with Physical Design implementation is a plus Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams Strong analytical/problem solving skills and pronounced attention to details Regards Divya Pandey LinkedIn: linkedin.com/in/divya-pandey-5345ba218 Mail Id: [email protected] -- Keywords: information technology golang Colorado Idaho ASIC Static Timing Analysis Engineer || Longmont, CO- Onsite [email protected] |
| [email protected] View All |
| 02:00 AM 05-Feb-25 |