| Hardware Engineering at Mountain View, California, USA |
| Email: [email protected] |
|
From: Srivalli, Fluxteksolutions [email protected] Reply to: [email protected] Job Title: Hardware Engineering and R&D - Silicon Verification Engineer 5- 150239-1 Location: Mountain View, CA Visa Status: Any Except OPT & CPT Exp: 12 years Silicon Verification is must 1. Minimum 12 years experience with SystemVerilog and UVM libraries including UVM Info 2. Minimum 10 years experience with code coverage and functional coverage (based off of SystemVerilog) 3. Minimum 5 years experience with formal methodologies Hard Skills Assessments Expected Dates that Hard Skills Assessments will be scheduled: ASAP week of 2/3/25. Hard Skills Assessment Process: The assessment process will include two 30-minute sessions with engineers on the team. Required Candidate Preparation: Candidates should have their SystemVerilog and UVM skills ready to demonstrate prepared prior to the assessment. The HSA(s) will include asking coding questions in both SystemVerilog and UVM. Summary: The main function of Silicon Verification Engineer is to be a part of the test-plan generation process, creating, testing, and implementing various verification plans. Job Responsibilities: Define, document, and implement a UVM verification environment including agents and scoreboards Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes Support post-silicon verification activities of the products working with design and product teams Skills: Proficient in using Verilog and VMM/OVM/UVM Experience in pre and post silicon verification test flow and automated test benches Effective communication, collaboration, and teamwork skills Education/Experience: Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or related degree required 12+ years of relevant experience required. Keywords: rlang California Hardware Engineering [email protected] |
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| 01:29 AM 06-Feb-25 |