| Hiring - Logic Design (RTL) Engineer - San Jose, CA at San Jose, California, USA |
| Email: [email protected] |
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Role: Logic Design (RTL) Engineer Location: San Jose, CA JOB DESCRIPTION Experience with high performance digital blocks. Prior experience of sigma-delta ADC will be very helpful. Proficient with Verilog-HDL & System Verilog coding. Understanding of high speed DSP applications, clock domain crossing will be helpful. Proficient with Cadence tools such as NCVerilog, NCSIM, Simvision. Experience with linting tools (i.e Spyglass) will be helpful. Independent, self-motivated with good analytical & communication skills. Tech node is not important for this position but if a person has worked on N7 that is good." -- Keywords: information technology wtwo California Hiring - Logic Design (RTL) Engineer - San Jose, CA [email protected] |
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| 02:41 AM 12-Mar-25 |