| Design Verification Engineer at Remote, Remote, USA |
| Email: [email protected] |
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http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=2322731&uid= From: Prabhat, VYZEINC [email protected] Reply to: [email protected] Job Description - LINKEDIN with 100+ conn || Design Verification Engineer - CPU Subsystem ( Must be in AUSTIN) Hybrid || Austin, TX Design Verification Engineer - CPU Subsystem Scope: Define verification plans & develop DV environments independently in System Verilog (SV)/UVM. Knowledge of C++ is preferred. Create & execute test plans to ensure the quality/reliability of the companies IP solutions. Expertise in System Verilog & UVM methodologies. Perform functional verification at the RTL level, including coverage analysis & improvement. Develop Universal Verification Components (UVCs) from scratch. Experience with Cache, NOC Interconnect verification is desirable. Knowledge of bus protocols AXI, CHI etc. are added advantage. Required: 7+ years of experience in DV & verification methodologies. Strong proficiency in System Verilog & UVM. Ability to work independently & drive projects to completion. Experience in IP development, particularly in DFD IP, is desirable. Excellent problem-solving & communication skills. Keywords: cplusplus Texas Design Verification Engineer [email protected] http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=2322731&uid= |
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| 06:22 AM 08-Apr-25 |