| Design Verification Engineer - CPU Subsystem at Austin, Texas, USA |
| Email: arbab@vizoninc.com |
|
From: Arbab Ahmed, Vizon Inc arbab@vizoninc.com Reply to: arbab@vizoninc.com Hello, Hope you are doing well. Job Description - Job Title: Design Verification Engineer - CPU Subsystem Location: Hybrid || Austin, TX Duration: 6+ months Scope: Define verification plans & develop DV environments independently in System Verilog (SV)/UVM. Knowledge of C++ is preferred. Create & execute test plans to ensure the quality/reliability of the companies IP solutions. Expertise in System Verilog & UVM methodologies. Perform functional verification at the RTL level, including coverage analysis & improvement. Develop Universal Verification Components (UVCs) from scratch. Experience with Cache, NOC Interconnect verification is desirable. Knowledge of bus protocols AXI, CHI etc. are added advantage. Required: 7+ years of experience in DV & verification methodologies. Strong proficiency in System Verilog & UVM. Ability to work independently & drive projects to completion. Experience in IP development, particularly in DFD IP, is desirable. Excellent problem-solving & communication skills. Keywords: cplusplus Texas Design Verification Engineer - CPU Subsystem arbab@vizoninc.com https://jobs.nvoids.com/job_details.jsp?id=2331192 |
| arbab@vizoninc.com View All |
| 05:11 AM 10-Apr-25 |