| PhysicalDesign Engineer || Bay Area, CA || Austin, TX || Onsite at Austin, Texas, USA |
| Email: [email protected] |
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http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=398153&uid= From: Bharathi, S2SSOFT [email protected] Reply to: [email protected] Hi, I am Bharathi from S2SSOFT, I hope you doing good. Kindly let me know if youre interested for the below position. Role: Physical Design Engineer Location: Bay Area, CA/Austin, TX (Onsite) Skills : InNovus tool experience Job description: Job Role Working on 10nm/7nm/5nm designs OR Lower Nodes with various customers for deployment. Expertise in solving custorner's problems for critical designs to achieve desired performance, area and power targets. Responsible to develop flow and methodology for doing placement, CTS and routing. Provide training and technical support to customers Job Requirement: Solid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations). Experience on hierarchical designs and/or Low Power implementation is an advantage. Experience on Synthesis, interfacing with RTL and implementation designers to achieve better quality of results. Experience on Floorplan design, including placement of hard-macros, padring, power grid and custom analog routes. Experience on Static Timing Analysis related activities (constraints development, parasitic extractions, sign-off requirements). Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing). Hands-on experience with FinFET technologies is an advantage Qualification: Typically requires minimum of 2-10 years of experience in Physical Design with mainstream P&R tools BE/B.Tech in Electronics and Communication (E&C) or Electrical or Telecom Engineering. ME/M.Tech in VLSI or Microelectronics is a plus Regards, Bharathi C Technical Recruiter Keywords: cprogramm access management rlang California Texas http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=398153&uid= |
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| 02:09 PM 14-Mar-23 |