| Design Verification Engineer at Mountain View, California, USA |
| Email: [email protected] |
|
http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=464786&uid= Hi , Hope everyone having a good time!! I have an exciting job opportunity. Job Title: Design Verification Engineer Location: Mountain View CA Duration- Long term contract Immediate Interview Technical Experience: Experience in System Verilog testbench development and UVM methodology is a must Must have hands-on experience with at least 2 SoC/Sub-System/IP verification projects, along with SV-UVM based testbench development for at least 3 year Hands-on experience on CPU(s) based SoC verification and writing/maintaining C-SV tests Hands-on experience with UVM/OVM and System Verilog through development of test bench components, generating directed and random stimulus, and coding cover points and assertions Experience in developing test and coverage plan, Verification environment and validation plan Experience in debugging design and driving coverage closure Experience in verification of AMBA protocols and one of the protocols like PCIe/HBM/DDR Knowledge of and basic working experience on C/C++ and Python based script development/maintenance Experience in Gate Level Simulation, Pre/Post Silicon Validation support Regards; Ankit Gautam +1 (678-659-9420) [email protected] Keywords: cprogramm cplusplus California http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=464786&uid= |
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| 07:55 PM 31-Jul-23 |