| Design For Test (DFT) Engineer :: Remote :: C2C :: USC, GC only at Remote, Remote, USA |
| Email: [email protected] |
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http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=815270&uid= From: Pravesh Kumar, Sibitalent [email protected] Reply to: [email protected] Position : Design For Test (DFT) Engineer Location : Remote Type : C2C/W2 Duration : 12+ Months Visa : USC, GC only Job Description: o Sub-chip & full-chip level DFT Insertions which primarily include Scan, ATPG, MBIST and associated simulations. o Retargeting block level test patterns to sub chip & full chip. o Person needs to be an expert at Scan ATPG, Stuck-at, at-speed insertions, boundary coverage, compression & retargeting flows using Mentor Tessent EDA tool. o Should have a good understanding of STA (Static Timing Analysis) & constraint generation. o Independently be able to debug mismatches with very little help/guidance. o Able to communicate clearly and work with other folks (esp. during initial ramp). o Document results/progress and provide timely updates. Purpose of this team design for logic, anything need to test out part (timing or simulations) Reason for the request Net new role Surrounding team & key projects o Sub-chip & full-chip level DFT Insertions which primarily include Scan, ATPG, MBIST and associated simulations. o Retargeting block level test patterns to sub chip & full chip. o Person needs to be an expert at Scan ATPG, Stuck-at, at-speed insertions, boundary coverage, compression & retargeting flows using Mentor Tessent EDA tool. o Should have a good understanding of STA (Static Timing Analysis) & constraint generation. o Independently be able to debug mismatches with very little help/guidance. o Able to communicate clearly and work with other folks (esp. during initial ramp). Document results/progress and provide timely updates. Motivators for this need Right skills Budget approved (Y/N) -Yes Typical task breakdown and operating rhythm o Dependent on where the project is o Focus on simulation o Quality clean up o focused more on design level insertion, meaning RTL coding Interaction level with sponsor/team Team/Sponsor: moderate/high Chance for extension later possible Expected working hours 40 hours a week Location Requirements & EC Details Remote Opportunity to work at Microsoft, new assignment from a Hardware perspective, they will gain more depth in their knowledge. There is a lot of engineering effort to be learned. Years of Experience Required 10+ years Degrees or certifications required experience is more important Disqualifiers o Low tenure o Large gap since working with the tools Best vs. Average o Previous MSFT experience o Person needs to be an expert at Scan ATPG, Stuck-at, at-speed insertions, boundary coverage, compression & retargeting flows using Mentor Tessent EDA tool. o Should have a good understanding of STA (Static Timing Analysis) & constraint generation. o Good written and verbal communication Performance Indicators o Meeting deadlines Thanks & Regards Pravesh Kumar Technical Recruiter Email : [email protected] Keywords: green card wtwo http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=815270&uid= |
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| 11:00 PM 01-Nov-23 |